Standard cells are the Rodney Dangerfield of digital IC creation - they get no respect - despite the profound impact they have on the performance, power consumption, area, and yield of a design. Standard-cell library development has been viewed as a black art, and ironically, is still often performed by hand. Faced with that time-consuming, expensive process, many semiconductor firms have opted to work with independent library vendors, purchasing customized libraries or using royalty based off-the-shelf libraries.

While these options are convenient in many cases, they provide limited optimization for design style, performance, power, area and yield. Furthermore, by forfeiting control over the layout, companies also sacrifice the knowledge of the design team as to how the libraries will be used. Additionally, many companies have yet to accept the concept of sharing confidential IP with competitors.

At the same time, new process technologies are arriving every six months, standard-cell designs are becoming more complex, and libraries are increasing in size and richness-growing from 200 to 300 cells a just few years ago to 500 cells or more today - with separate libraries for high performance, minimum area and low power. While a technical eye correctly views the use of "one size fits all" off-the-shelf libraries as a compromise, the combined pressures of resource constraints and time-to-market concerns exert a great deal of influence over how libraries are created.

Typical solutions

How then are semiconductor companies to gain the advantages of custom-tailored standard-cell libraries, given the rising design complexity and decreasing ability to find layout engineers?

One possible solution to the problem is becoming a reality. The use of "liquid libraries"-libraries whose core cells are created by an experienced design team, but whose richness is created on an as-needed basis-moves most of the library creation process into the EDA synthesis and place-and-route flow, where the design expertise is already concentrated.

The liquid library standard-cell place-and-route flow is a modified version of a typical SPR flow. The typical flow includes the following steps, some of which may be combined, depending on the tools:

1. Synthesis from RTL to gates
2. Placement of gates
3. Detailed routing of gates
4. Resizing of gate drive strength given the detailed routing
5. ECO placement
6. ECO routing

The SPR tools use the library in each phase of the flow. In the typical SPR flow, the library is a static collection of cells. The cells are defined before any RTL is synthesized, based on the library designers' expectations of the eventual requirements. The library designer predetermines the trade-offs between power, area, cycle-time, and manufacturability (see Figure 1).

Figure 1 - Where we are

The traditional synthesis flow incorporates static libraries at various phases in the process, libraries that come with pre-determined constraints.

However, as the design progresses, the requirements for the library are continuously changing. Furthermore, different portions of the design may have different requirements. For example, a design may be area-critical-requiring an area-minimized library. However, one of the blocks may dictate the overall cycle time of the entire design. Given the design compromises often needed for area-sensitive layout, the area-minimized library will probably not meet the desired cycle time. In addition, with a typical static library, some cells may need to be added by hand to assist the critical timing paths.

Another option is to redesign the entire library to improve performance, but this can result in significant setbacks in area utilization and power. Ideally, each block will be designed using a library that is optimized for that block's requirements. However, if the library is being hand crafted, or only partially automated, this optimization requires a prohibitive amount of additional design-time.

New ideas

The liquid library concept helps to solve these design dilemmas. In a liquid library flow, the library of cells is created automatically as needed. The library is optimized for the particular design as well as for the requirements of the specific block being created. The steps for a liquid library SPR flow are as follows:

1. Synthesis from RTL to gates, using a seed library
2. Placement of gates
3. Detailed routing of gates
4. Resizing of gate drive strength given the detailed routing
5. Building the library cells
6. ECO placement
7. ECO routing

The key differences between a typical flow and a liquid library flow are in Steps 1 and 4 above. In those steps of the process, instead of giving the synthesis and place-and-route tools a static library, the tools use a liquid library, which represents the range of all possible cells. Depending on the SPR tools in use, the liquid library can then be represented as a very large set of individual cells, or the library can have a more abstract representation of the possible cells. Once the synthesis tool has selected the final cells during Step 4, those cells are built and characterized dynamically. The liquid library flow then adds the library cell-building step (see Step 5).

Figure 2 - Where we're going

The concept of liquid libraries allows automatic generation of optimized cells, which responds to the design in progress.

The advantages of the liquid library approach can be significant. In the initial synthesis stage, an essentially unlimited set of cells is now available. Therefore, the library is much richer and more useful to the synthesis tool. Furthermore, during the resizing of the cells, the optimum drive-strength cell can be selected as needed (see Figure 2).

For example, suppose the delay of a 1X drive-strength gate driving itself is one time unit (t). Then suppose that a 1X gate is driving a gate that needs to drive a 36X load. The delay through the two gates is expressed as:

S + 36/S

where S is the drive-strength of the middle gate.

If a static library designer includes a range of drive strengths for this gate (for instance, 1X, 3X, and 9X gates), the best delay through the pair of gates would be:

9 + 36/9 = 13 t

using the 9X gate for the middle gate.

Using a liquid library, however, the optimum drive-strength gate of 6X is automatically created on the fly, yielding a 12 t delay-or an 8 percent improvement in cycle-time. The 6X gate also uses significantly less power than the 9X gate.

Now suppose that the static library only contained the 1X version of the gate, which is a common problem with many cells in static libraries. In this case, the delay through the pair of gates would be:

1 + 36/1 = 37 t

This is more than triple the optimum delay. If the target cycle time is 12 t, there is no solution using the static library. Even restructuring the logic into different gates will probably not result in a solution. The liquid library strategy speeds design closure by generating the cells as needed.

SPR tool requirements

The synthesis tool must be able to handle the large potential libraries that a liquid library represents. This can be accomplished by abstracting the cells, or by simply having a very large set of discrete cells. The major advantages of a liquid library stem from its ability to represent a rich set of library elements.

Similarly, the place-and-route tool must be able to work with cell layouts that don't necessarily represent the final layouts that will be used in the block. Once the final liquid library has been frozen, the place-and-route tool must be able to make engineering change orders (ECOs) to the final placement and routing to produce the final detailed placement and routing.

In order to be able to generate the liquid library as part of the flow, the library generation software must be completely automated - able to run without human intervention. Furthermore, the library generation must guarantee completion, regardless of the cells needed by the SPR flow.

Because the place-and-route tool will be making ECOs to the final design, the liquid library generation must be repeatable and consistent. Practically speaking, this means the cell layout must be similar throughout a family of gates.

For example, if the 6X version of a gate is dramatically different from the 6.2X version of the gate, the place-and-route tool may oscillate between the solutions and result in a non-optimum selection - or, worse yet, may never complete a solution at all. To prevent this problem, the liquid library generation software must guarantee a consistent answer.

Important considerations

A place and maze-route solution to library generation is typically not well suited for liquid libraries because the synthesis solutions are generally chaotic in nature.

The inconsistent behavior associated with such solutions makes it difficult to produce consistent results. Also, they generally can't guarantee completion for any given cell. This differs from block-level place-and-route because the cell-level wire connections (the transistor terminals) are much denser than the block-level wire connections (I/O ports of cells).

It's possible to automate the library creation process in a way that makes liquid libraries possible. For example, the Prolific, Inc. tool (Newark, CA) uses generators to guarantee completion as well as to guarantee repeatable and consistent results. The generators build the layout topologies in a pre-determined fashion. The layout topologies are then compacted according to the target design-rules to create the final layouts. Because the generators build the layout topologies in a pre-determined fashion, the resulting layouts can be guaranteed to fit within a certain specification.

By reducing the number of standard cells that must be created for a device to be successfully created, liquid libraries offer a way to make library creation more manageable - even as the libraries themselves become larger. By allowing library designers to focus on a core set of seed cells, and creating additional cells as they are needed, liquid libraries can help to make standard-cell IP more useful, and thus more valuable.

Paul de Dood is president and founder of Prolific, Inc. (Newark, CA). Previously, he managed the library and full-chip integration group for the Sun Microsystems' UltraSparc and UltraSparc-II product lines.

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